The Ferrite Bead Delusion in High-Speed Power Delivery Networks
Blindly adding ferrite beads to high-speed power rails causes harmful anti-resonance and severe voltage droop during high current steps.
A classic piece of legacy hardware advice is to throw a ferrite bead onto the power supply rail of every high-speed IC to choke out high-frequency noise. While this worked well in the era of slow edge rates, blindly placing ferrite beads into modern, low-voltage high-speed Power Delivery Networks (PDNs) is a recipe for severe voltage ripple and system instability.
A ferrite bead is an inductive component that exhibits high impedance at specific high frequencies. When placed in series with a power rail, it effectively blocks high-frequency current from moving back and forth. However, modern high-speed processors require massive, ultra-fast steps in current (di/dt) when transitioning from an idle state to full processing load. The series inductance of the ferrite bead blocks the board's bulk bypass capacitors from delivering this instantaneous current to the IC.
This restriction causes a massive voltage droop at the chip's power pins. Furthermore, the interaction between the inductive ferrite bead and the capacitive local bypass array forms an unintended high-Q LC resonant circuit. This anti-resonance peak spikes the overall PDN impedance at specific frequencies, amplifying rather than suppressing power supply noise. Instead of relying on beads, drop the series inductance entirely. Build a low-impedance PDN by grouping ultra-low ESR ceramic capacitors close to the power pins with short, wide traces and dedicated power plane stitching.